Design, implementation, and evaluation of a field-programmable gate array-based wireless local area network synchronizer

Synchronization is a critical operation required by majority of wireless receivers. This paper presents the design, implementation, and evaluation of an orthogonal frequency-division multiplexing baseband packet synchronizer deployed on a field-programmable gate array (FPGA). Packet detection, carrier frequency offset estimation/correction, and time synchronization are all performed in the time domain by processing samples before the fast Fourier transform computation on the receiver. We propose techniques to reduce the area complexity of the arithmetic computations while maintaining the performance of existing approaches. FPGA implementation results are reported, and the design is evaluated by simulation under additive white Gaussian noise channel conditions. Copyright © 2011 John Wiley & Sons, Ltd.